In recent years, it is desired that failure detection be performed in an LSI for automobile to prevent a failure of the system before causing a serious accident. As a function to detect a failure, watchdog timers are well known. Use of a watchdog timer is such that a CPU periodically clears the timer, and if the timer overflows, it is determined that the CPU has failed. However, the watchdog timer does not detect a failure of the CPU directly, and thus there is a possibility of overlooking a failure.
There is also a measure such that a calculation for detection is performed and a calculation result is checked. However, when a problem occurs in a circuit controlling the flow of instructions, the program for detection may freeze when it is executed, and there is a possibility that the calculation result is not obtained.
Further, Japanese Laid-open Patent Publication No. H05-2654 discloses a failure detection method for microcomputer aiming at improving a failure detection probability in a microcomputer by using a simple structure and further reducing the time from occurrence of a failure to detection of the failure.
Moreover, Japanese Laid-open Patent Publication No. 2001-188688 discloses a freeze detection circuit for microcomputer aiming at detecting processing of an erroneous code.
Patent document 1: Japanese Laid-open Patent Publication No. H05-2654
Patent document 2: Japanese Laid-open Patent Publication No. 2001-188688